1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a recessed source and drain structure formed by selective epitaxial growth of a compound semiconductor material such as silicon-germanium (SiGe) and a method of manufacturing the same.
2. Discussion of Related Art
Recently, as electrical devices are being made ever smaller, thinner and lighter, semiconductor devices are rapidly being made smaller and thinner. For example, reduction in the size of complementary metal-oxide semiconductor (CMOS) transistors has led to considerable progress in increasing the operating speed and degree of integration of devices. However, a CMOS transistor having a gate width of 65 nm or less is hard to manufacture because various problems may occur in the manufacturing process. In order to solve the problems, various methods of applying tension and compressive stress to a silicon channel constituting a transistor to enhance electron and hole mobility and increase driving current have been suggested.
According to one of the methods, a SiGe layer in which stress is reduced is grown to have minimum defects under both sides of a silicon channel. It is known that the electron mobility of an outwardly strained silicon channel formed on a SiGe single crystal is higher than that of a bulk silicon layer. In addition, it is known that the hole mobility of a compressively strained SiGe layer having a high germanium content is five or more times faster than that of a bulk silicon layer.
According to another method, after a transistor has been manufactured, a silicon-nitride layer having high stress is grown on the transistor, and thereby stress is applied to a silicon channel. It is known that electron mobility increases by about 20% when the method is applied to an n-type metal-oxide semiconductor field effect transistor (nMOSFET). Most lately, a method that forms a recessed SiGe source and drain in a p-type MOSFET (pMOSFET) and thereby improves hole mobility has been suggested. It is known that hole mobility increases by about 50% and driving current increases by about 25% when the method is applied.
According to the most general method of forming a recessed SiGe source and drain, a gate spacer is formed, a substrate is etched to a desired depth by a plasma dry-etching method, and a SiGe layer is selectively formed in source and drain regions by a chemical vapor deposition method.
Hereinafter, a conventional recessed source and drain structure will be described with reference to appended drawings. FIGS. 1A to 1D are side cross-sectional views illustrating a manufacturing process of a semiconductor device having a conventional recessed source and drain structure.
Referring to FIG. 1A, a gate oxide layer 12 is formed on a semiconductor substrate 11 which constitutes a transistor 10, and a gate electrode 13 is formed on the gate oxide layer 12. Gate spacers 14 are formed on sidewalls of the gate electrode 13, and isolation layers 15 are formed at outer regions surrounding an element in order to isolate the element from adjacent elements, e.g., transistors.
Referring to FIG. 1B, source and drain regions 16 are formed on the semiconductor substrate 11 of FIG. 1A using a plasma dry-etching method. The source and drain regions 16 are etched to a predetermined depth. In general, when the plasma dry-etching method is used, defects may occur on a silicon surface, and thus there are defects 16a on the surface of the source and drain regions 16 due to the etching.
Referring to FIGS. 1C and 1D, after the plasma dry-etching process, SiGe single crystals are selectively grown so that source and drain electrodes 17 are formed on the source and drain regions 16. Subsequently, nickel-silicide layers 18 are formed on the SiGe single crystals and the gate electrode 13.
However, when the plasma dry-etching method is used to form the recessed SiGe source and drain regions through the process described above, defects may occur on the silicon surface and cause related defects on an interface on which the SiGe single crystals are formed. Therefore, in order to minimize the defects of the SiGe single crystals, low ion implantation energy is suggested together with a chemical dry-etching method. However, since the source and drain regions toward a silicon channel may be formed in a bird's beak shape rather than perpendicular to the surface of the silicon, stress cannot be uniformly transferred to the silicon channel.
In addition, according to the method described above, the source and drain regions are formed after the gate spacers are formed. Therefore, the distance between the source and drain becomes larger than the gate width by the distance of both spacers, so that it is hard to transfer stress to the silicon channel. More specifically, the source and drain regions are formed larger than the gate width, and thus a stress value in the silicon channel decreases compared to when the source and drain regions are positioned under both sides of the gate.